DATA SHEET
I3C Protocol Validation Suite - Specifications Datasheet - I3C Protocol Validation Suite
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Product Details
- Overview
- Functional Coverage
- Parametric Coverage
- Features
- FAQ
Overview
MIPI I3C is a scalable, medium-speed, utility, and control bus interface for connecting peripherals to an application processor, streamlining integration, and improving cost efficiencies. It gives developers unprecedented opportunities to craft innovative designs for any mobile product—from smartphones to wearables, to systems in automobiles.
As a part of product validation, it’s important to validate the product’s conformance against the protocol specification to ensure the interoperability of the product. As the complexity of the protocol and product increases, the validation time of the protocol interfaces also increases which in turn reduces the RTM. Performing the protocol conformance testing in the traditional way needs a lot of time and effort.
Soliton’s I3C Slave Validation Suite is an off the shelf validation tool using NI’s PXI platform, which helps to validate the devices’ compliance with the timing and electrical specifications of the MIPI I3C protocol. The tool can also validate the device’s tolerance to and recovery from a variety of I3C faults & exceptions and provides a comprehensive set of reports. Users have claimed that using this automated solution for I3C Slave Validation has brought down the test time/ validation time from a few weeks to a couple of days.
Functional Coverage
MODES
- I3C SDR mode (15 MHz)
- I3C HDR-DDR mode (15 MHz)
- Legacy I2C Mode (5 MHz)
FUNCTIONAL TESTS
- Register Write (Legacy I2C /SDR/HDR)
- Register Read (Legacy I2C /SDR/HDR)
- Write N Bytes (Legacy I2C /SDR/HDR)
- Read N Bytes (Legacy I2C /SDR/HDR)
- Write N – Read N Bytes (Combined Format) (Legacy I2C /SDR/HDR)
- Hot-Join Functional Test*
- IBI Functional Test*
- IBI Interrupt Spacing Tests
- Master Clock Stalling
PROTOCOL FEATURES
- Dynamic/Static Addressing
- Direct and Broadcast CCC Commands
- START / STOP Conditions
- Address Header and Transition Bit
- HDR DDR Restart and Exit Patterns
- Slave Reset Pattern
- Group Slave Addressing
FAULT TESTS
- Induce SDR Errors (S0-S5)
- Induce HDR DDR Errors
- Skip Start / Stop / Repeated Start
- Skip HDR Restart / HDR Exit
- Add clocks from address/data bytes
- Skip clocks from address/data bytes
- Induce Parity/Preamble Errors
- Induce Errors in CRC5 Calculation
- Any custom faults in SDR/ HDR DDR transactions and can check if the slave is able to recover from the faults.
Parametric Coverage
I2C Legacy Timing Parameters
- fSCL SCL Clock Frequency
- tSU_STA Setup time for Repeated Start
- tHD_STA Hold time for a (Repeated) start
- tLOW SCL Clock Low Period
- tHIGH SCL Clock High Period
- tSU_DAT Data Setup Time
- tHD_DAT Data Hold Time
- trCL SCL signal Rise time
- tfCL SCL signal Fall time
- trDA SDA signal Rise time
- tfDA SDA signal Fall time
- tSU_STO Setup time for Stop
- tBUF Bus Free time between a Stop and a Start
- tSPIKE Pulse width of spikes to supress
- tDIG_H Digital SCL Clock High Period
- tDIG_L Digital SCL Clock Low Period
Electrical IO Parameters
- VIL Low-Level Input Voltage
- VIH High-Level Input Voltage
- Vhys Schmitt Trigger Inputs Hysteresis
- VOL Output Low Level
- VOH Output High Level
I3C Push-Pull Timing Parameters
- fSCL SCL Clock Frequency
- tLOW_PP SCL Clock Low Period
- tHIGH_PP SCL Clock High Period
- tSCO Clock in to Data out for slave
- tCR SCL Clock Rise Time
- tCF SCL Clock Fall Time
- tHD_PP SDA signal Data Hold in Push-pull mode
- tSU_PP SDA signal Data Setup in Push-pull mode
- tCASr Clock after Repeated start condition
- tCBSr Clock before Repeated start condition
- tDIG_H Digital SCL Clock High Period
- tDIG_L Digital SCL Clock Low Period
Open-Drain Timing Parameters
- tLOW_OD Low period of SCL clock
- tHIGH_OD High period of SCL clock
- tfDA_OD Fall time of SDA signal
- tSU_OD Data setup time during open-drain mode
- tCAS Clock after start condition
- tCBP Clock before stop condition
- tAVAL Bus Available Condition
- tIDLE Bud Idle Condition
- tDIG_H Digital SCL Clock High Period
- tDIG_OD_L Digital SCL Clock Low Period
Features
Features of I3C Protocol Validation
- Simple, Flexible, Modular, and Light Bench Setup
- Easy to use I3C Protocol Exerciser and Debugger to perform various I3C transactions with controllable timings/voltage levels
- Protocol compliance testing with zero coding
- Comprehensive reporting feature to report the test pass/fail reports
- Generates Full Compliance reports in less than 2 hours
- Reproduce failure cases in a few clicks
- Easy to build and test custom device-specific tests
- Automation Capability from external programming environment/automation frameworks like LabVIEW, C#, Python, TestStand, etc
- Leverage Soliton’s experience in protocol validation and debugging.
FAQ
What kind of engagement models is offered for I3C Validation?
We offer 2 engagement models. In the First mode, the user can purchase a license of the I3C Slave Validation Suite and do the validation inhouse. In the second mode, the user can send us 3 DUT's, we will do the validation and send the test reports in 3 working days.
Do I always need to test for full I3C compliance?
No, this is not always the case. If your customer has a very narrow use case, or your chip’s I3C IP is the same as a previously tested chip, then it is possible that you do not need the extensive validation that our service/suite provides.
Can't I build a home-grown solution instead?
While this is certainly an option, we expect that it will take a highly experienced automation engineer between 3-6 months to create a first version of a similar tool. To create a robust and flexible tool takes experience, and we have been improving this tool over the last 3 years since release. We believe it is worth the cost to skip the learning curve and avail our comprehensive report or validation suite.
What else can I do with NI's PXI chassis/modules?
The 6570 module is a general-purpose programmable pattern generator and acquisition device with deep memory. It can be programmed using LabVIEW or other programming languages to emulate any synchronous digital protocol with 5ns resolution and 39ps line skewing resolution. NI’s PXI chassis supports high bandwidth and synchronization-friendly control and read back from a huge variety of digital, analog, and special-purpose modules in a compact form factor.
What version of MIPI spec is supported?
Currently, the tool supports MIPI I3C version 1.0 and MIPI I3C Basic 1.0
Whether the tool can be readily used for validation?
Yes, The tool comes with readily available test scripts that can be used for validation after entering the device-specific details.
Can I build custom tests on top of I3C protocol?
The tool comes with a flexible test editor that allows the user to create custom test cases using the I3C functions provided
Technical Documentation
Soliton’s I3C Slave Validation Suite is an off the shelf validation tool using NI’s PXI platform, which helps to validate the devices’ compliance with the timing and electrical specifications of the MIPI I3C protocol. It contains the below components.
- NI PXIe 657x – Digital Pattern Generation Card with the PXIe Chassis setup
- Soliton PVS Interposer Board
- Oscilloscope – For performing voltage measurements
- Soliton I3C Slave Validation Suite Software compatible with Windows OS (Win 10)
For more details, download the datasheet.
I3C Protocol Validation Suite - Specifications Datasheet - I3C Protocol Validation Suite
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Hardware
Soliton’s I3C Slave Validation suite is based on the NI – PXI Platform and the NI part configuration lists the hardware required to perform the validation
The Solution also contains a Soliton Interposer Board for signal conditioning purposes. The Connection Details of the board is given below
Support & Training
For any queries, contact us at [email protected]. We will respond within 1 Business day