SPMI Protocol Validation Service

Get a detailed SPMI Protocol Compliance Test Coverage Report!

SPMI (System Power Management Interface) is a MIPI (Mobile Industry Processor Interface) standard with 2-wire synchronous serial, bi-directional interface that connects the integrated Power Controller (PC) of a System-on-Chip (SoC) processor system with one or more Power Management Integrated Circuits (PMIC) voltage regulation systems.

Soliton offers services to emulate SPMI Master & Slave which could be used to validate the SPMI bus interface on your chip. We will validate both the timing and functionality of your SPMI Master or Slave devices. The test solution is compatible with SPMI bus specification version 2.0 and supports NRCS (Non-Request Capable Slave) devices. The solution can skew bus timing parameters, sweep bus voltage levels, induce spikes/glitches on the communication bus, induce packet formation faults and measure bus timing parameters.

Customers can ship Soliton three DUT boards featuring their SPMI Master or SPMI Slave Device and Soliton will send a detailed report that has results for the below tests. Though the pricing button below only indicates the pricing for the SPMI Validation service offered by Soliton, Soliton is also offering the software product that enables customers to perform the validation on their end using National Instruments PXI-6570 and a benchtop oscilloscope. The product is currently in beta mode. Interested parties can contact us using the comments in the below buttons if interested in this option and we will quote you this option based on the understanding of hardware you already own it.


  1. Ability to support following SPMI command sequences

    – Register 0 Write
    – Register Write (1 data byte)
    – Register Read (1 data byte)
    – Extended Register Write (N data bytes, 8-bit address)
    – Extended Register Read (N data bytes, 8-bit address)
    – Extended Register Write Long (N data bytes, 16-bit address)
    – Extended Register Read Long (N data bytes, 16-bit address)

    SPMI Bus Protocol Register Write Command Sequence

    SPMI Bus Protocol Register Read Command Sequence

  2. Supports two speed classes with the below range of supported SCLK frequencies

    Low Speed (LS): 32kHz to 15MHz
    High Speed (HS): 32kHz to 26MHz

  3. Ability to configure & sweep bus timing parameters to the Min & Max range

    TSCLKOH – Clock output high time
    TSCLKOL – Clock output low time
    TD – Time for Data Output valid from Clock rising edge
    TSDATAZ – Data drive release time
    configure & sweep bus timing parameters to the SPMI Bus Protocol Min & Max range

  4. Measure Rise & Fall time at 5ns resolution

    TSCLKOTR (rise) – Clock output transition time (rise)
    TSCLKOTR (fall) – Clock output transition time (fall)
    TSDATAOTR (rise) – Data output transition time (rise)
    TSDATAOTR (fall) – Data output transition time (fall)

  5. Support for programmable bus voltage levels

    VTP – Positive going Threshold voltage (VIH)
    VTN – Negative going Threshold voltage (VIL)
    VH – Hysteresis voltage

  6. Ability to induce glitches/spikes in SCLK & SDATA lines
  7. Ability to induce faults in SPMI Packet formation

    – Skip SSC (Sequence Start Condition)
    – Skip a bit in Command/Address/Data Frame
    – Send Invalid Command/Address Frame
    – Skip a Data Frame
    – Send additional bit in Command/Address/Data Frame
    – Skip Parity Bit in Command/Address/Data Frame
    – Induce Parity Error in Command/Address/Data Frame
    – Induce Bus Timeout with SDATA & SCLK pulled LOW

  8. Ability to add General Command Sequences

    – Authenticate, Shutdown, Reset, Sleep and Wakeup

Please contact [email protected] for more details.