UART Protocol Validation Service
Soliton offers services to emulate UART Master & Slave which could be used to validate the UART bus interface on your chip. We provide solutions to generate UART packets to communicate with your Master/Slave device and characterize the device by skewing the communication baud rate, varying bus voltage levels, inducing spikes/glitches on the communication bus, inducing faults in the communication like frame error, parity error & bit error.
UART (Universal Asynchronous Receiver Transmitter) is an Asynchronous Serial communication protocol. The data is not synchronized with a clock instead the data bits are transmitted with pre-defined baud rate and also appended with synchronization start & stop bits. It uses two wire interface (Tx & Rx) to communicate between devices.
Basic UART Packet Format
– Simplex : one direction only, transmitter to receiver
– Half Duplex : devices take turns transmitting and receiving
– Full Duplex : both devices send and receive at the same time
– Write Byte (1 byte)
– Read Byte (1 byte)
– Write Block (n bytes)
– Read Block (n bytes)
– Number of Data bits (5, 6, 7, 8, 9)
– Parity (NO, Even, Odd)
– Stop Bit (NO, 1 , 2)
1200, 2400, 4800, 9600, 19200, 38400, 57600 and 115200 bits/s
– Frame Error – Missing Stop bit
– Parity Error – Send Invalid Parity bit
– Send invalid data – bit flip
– Send additional bit
– Skip a bit
Parity error, Frame error (missing stop bit & Break condition)
VIL – LOW-level input voltage
VIH – HIGH-level input voltage
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