UART Protocol Validation Service

Soliton offers services to emulate UART Master & Slave which could be used to validate the UART bus interface on your chip. We provide solutions to generate UART packets to communicate with your Master/Slave device and characterize the device by skewing the communication baud rate, varying bus voltage levels, inducing spikes/glitches on the communication bus, inducing faults in the communication like frame error, parity error & bit error.

UART (Universal Asynchronous Receiver Transmitter) is an Asynchronous Serial communication protocol. The data is not synchronized with a clock instead the data bits are transmitted with pre-defined baud rate and also appended with synchronization start & stop bits. It uses two wire interface (Tx & Rx) to communicate between devices.

Basic UART Packet Format
Universal Asynchronous Receiver Transmitter (UART) Protocol Validation Service

UART Validation Features:

  1. Support for simplex, half duplex & full duplex communication modes

    – Simplex : one direction only, transmitter to receiver
    – Half Duplex : devices take turns transmitting and receiving
    – Full Duplex : both devices send and receive at the same time

  2. Simple Read – Write Communication APIs supporting ‘n’ bytes

    – Write Byte (1 byte)
    – Read Byte (1 byte)
    – Write Block (n bytes)
    – Read Block (n bytes)

  3. Ability to configure UART communication settings

    – Number of Data bits (5, 6, 7, 8, 9)
    – Parity (NO, Even, Odd)
    – Stop Bit (NO, 1 , 2)

  4. Ability to configure and sweep Baud Rate in fine steps to check the tolerance range

    1200, 2400, 4800, 9600, 19200, 38400, 57600 and 115200 bits/s

  5. Ability to configure and sweep idle time between two UART packets
  6. Configure the bit & byte order (LSB first / MSB first)
  7. Ability to induce faults in Command packets

    – Frame Error – Missing Stop bit
    – Parity Error – Send Invalid Parity bit
    – Send invalid data – bit flip
    – Send additional bit
    – Skip a bit

  8. Ability to induce glitches/spikes in Command packets
  9. Ability to detect & report errors in Response packets

    Parity error, Frame error (missing stop bit & Break condition)

  10. Ability to generate Break condition & Reset
  11. Allows programmable bus voltage levels

    VIH – HIGH-level input voltage

  12. Measure Baud Rate error in Response packets
Please contact [email protected] for more details.