PXI-based SPI Protocol Validation Suite & Service

Generate a SPI Validation Report in minutes for your chip!

Soliton’s SPI Validation Suite allows users to verify SPI protocol timings and spec compliance and perform break-the part-validation of the SPI interface for any SPI Slave Device. The suite lets users configure & skew/shmoo bus timing parameters, induce glitches, induce packet formation faults, sweep voltage parameters and measure bus timing parameters. If one wants to use LabVIEW to perform SPI Validation, the suite natively supports that. However, the suite can be accessed as an engine from any programming language using our interface APIs (DLLs).

The suite can be used to generate a timing, syntax, and fault tolerance report for any SPI Slave Device within a matter of minutes.  Alternatively, customers can also ship 3 DUT boards containing their desired slave device to Soliton Technologies and we will characterize the DUT and send the customer a comprehensive SPI Test Report, within a cycle time of 1 week.

SPI (Serial Peripheral Interface) is a synchronous, 4-wire serial communication protocol. The four signals are
        1. Chip Select (CS) [also called Slave Select(SS)]
        2. Serial Clock (SCLK)
        3. Master Output Slave Input (MOSI)
        4. Master Input Slave Output (MISO)

SPI devices communicate with each other using a master-slave architecture. SPI is a single-master, multiple-slave communication protocol. Multiple slaves are supported through individual Chip Select (CS) / Slave Select (SS) lines.

Pricing for SPI Protocol Validation Suite and for SPI Validation Service

We offer solutions under below categories.
SPI Validation Software Suite

The customer gets the SPI Protocol Validation Software Suite with a single site perpetual license. The suite includes SPI Test Scripts with which user could run compliance test on their SPI Slave device and generate SPI Validation report.

SPI Validation Report

The customer can ship* 3 DUT boards containing their desired SPI Slave device to Soliton Technologies and we will characterize the SPI Slave at room temperature and send a comprehensive SPI Validation report electronically, within a cycle time of 1 week.

* Soliton Technologies Pvt Ltd, #305, Tidel Park, Aerodrome Post, Coimbatore, India – 641014
Hardware supported by Soliton's SPI Protocol Validation Suite (The hardware emulates SPI master):

NI PXI High Speed Digital IO (HSDIO) – PXIe 6555 or 6556
(support for PXIe 6570 / 6571 is in pipeline)
We also have a separate PXI FlexRIO based solution for SPI Slave emulation which customers can contact us about.

Features of PXI based SPI Protocol Validation Suite
  1. Allows user to configure and sweep each bus timing parameter from the Min to the Max range

    – SCLK Frequency (Hz)
    – SCLK High (ns)
    – SCLK Low (ns)
    – CS Lead (ns)
    – CS Trail (ns)
    – CS Idle Start (ns)
    – CS Idle End (ns)
    – MOSI Setup (ns)
    – MOSI Hold (ns)

    Soliton's SPI Validation suite allows user to configure and sweep each bus timing parameter from the Min to the Max range
  2. Software can generate signals up to a SPI Clock frequency of 100MHz
  3. Allows user to configure the byte order (LSB first / MSB first)
  4. Allows user to configure Clock Phase & Clock Polarity

    SPI Parametric Validation tool allows user to configure SPI Clock Phase & Clock Polarity

  5. Allows programmable bus voltage levels

    VIL – LOW-level input voltage
    VIH – HIGH-level input voltage

  6. Provides ability to induce glitches/spikes in CS, SCLK & MOSI lines
  7. Provides ability to induce faults in SPI Read/Write Communication

    – Send additional clock bit
    – Skip a clock bit
    – Skip Chip Select(CS) assertion
    – Invert the Clock Polarity & Clock Phase
    – Send invalid Register Address, invalid Data Byte

  8. Supports simple file based SPI pattern generation

    Since API allows for some variation in how a packet is formed, the software suite accommodates this by allowing the user to define the SPI Read-Write communication pattern in a CSV file. The suite reads the pattern file and replaces the user input like Address/Write Byte and bursts the SPI pattern.

    The suite reads the pattern file and replaces the user input like Address/Write Byte and bursts the SPI pattern.

    SPI Validation software suite accommodates some variation in how a packet is formed by allowing user to define the SPI Read-Write communication pattern in a csv file
  9. Simple Read – Write Communication APIs supporting ‘N’ bits and ‘N’ bytes

    – Write Register (1 byte)
    – Read Register (1 byte)
    – Write Block (n bytes)
    – Read Block (n bytes)
    (The software suite allows user to configure SPI pattern file for each of the above communication APIs)

  10. Provides option to easily add any dynamic calculation field to the SPI pattern

    Say, if the pattern has CRC field which must be calculated based on Address & Data field and embedded into each packet, the software suite provides an option to enable this.

Test Plan Editor – Test Plan Editor allows users to create Test Scripts by drag & drop of the Test steps in a sequence, and to configure the test parameters. The SPI Tester comes with all the Test Scripts that are needed for doing SPI compliance tests. If the device contains any special wakeup process, or if the test has to extended beyond the SPI spec, the user can script and then execute the test.

The SPI Validation tool comes with all the Test Scripts that are needed for doing SPI compliance tests.

SPI Compliance report – The tool creates a compliance report for each test parameter at the end of script execution

PXI based SPI Validation software tool creates a compliance report for each test parameter at the end of script execution