SMBus (Signal Management Bus) Validation Service

Soliton can generate a full fledged timing, voltage, clock stretch behavior and fault tolerance report for the SMBus interface on a chip. The solution can skew bus timing parameters, sweep bus voltage levels, verify and measure clock stretching, induce bus timeout, induce spikes/glitches, induce packet formation faults and measure bus timing parameters. Customers can ship 3 DUT boards containing their desired slave device to Soliton Technologies and we will characterize the DUT and send the customer a comprehensive SMBus Validation Report within a cycle time of 1 week.

Generating a full fledged timing, voltage, clock stretch behavior and fault tolerance report for the SMBUS interface on a chip

Validation Features:

  1. Ability to configure and sweep each bus timing parameter from the Min to the Max range

    FSMB – Operating Frequency
    TLOW – Clock low period
    THIGH – Clock high period
    THD:DAT – Data hold time
    TSU:DAT – Data setup time
    TBUF – Bus free time between Stop and Start Condition
    THD:STA – Hold time after (Repeated) Start Condition
    TSU:STA – Repeated Start Condition setup time
    TSU:STO – Stop Condition setup time
    TTIMEOUT – Detect clock low timeout
    TLOW:SEXT – Cumulative clock low extend time (slave device)
    TLOW:MEXT – Cumulative clock low extend time (master device)

  2. Supported data transfer formats

    – Send Byte
    – Receive byte
    – Write Byte
    – Read Byte
    – Write Word
    – Read Word
    – Block Write
    – Block Read
    – Process Call
    – Block Write Block Read Process Call

  3. Support for 7-bit and 10-bit slave addressing
  4. Configurable Packet Error Checking (PEC) mechanism
  5. Support for Programmable bus voltage levels

    VIL – LOW-level input voltage
    VIH – HIGH-level input voltage

  6. Sweep and measure Rise time and Fall time

    TF – Clock/Data Fall Time
    TR – Clock/Data Rise Time

  7. Ability to induce faults in the communication

    – Skip a clock bit
    – Send additional clock bit
    – Skip START/STOP/RP-START/BYTE/ACK
    – Send NACK instead of ACK for a Read Byte
    – Send ACK instead of NACK for last Read Byte
    – Send incorrect PEC byte
    – Send invalid Data byte

  8. Ability to detect and allow clock stretching by the device.
  9. Ability to stretch the Clock low to induce clock stretching and bus timeout