SMBus (Signal Management Bus) Protocol Validation
Soliton’s SMBus validation Suite can generate a full-fledged timing, voltage, clock stretch behavior and fault tolerance report for the SMBus interface on a chip. The solution can skew bus timing parameters, sweep bus voltage levels, verify and measure clock stretching, induce bus timeout, induce spikes/glitches, induce packet formation faults and measure bus timing parameters. Customers can also ship 3 DUT boards containing their desired slave device to Soliton Technologies and we will characterize the DUT and send the customer a comprehensive SMBus Validation Report within a cycle time of 1 week.
FSMB – Operating Frequency
TLOW – Clock low period
THIGH – Clock high period
THD:DAT – Data hold time
TSU:DAT – Data setup time
TBUF – Bus free time between Stop and Start Condition
THD:STA – Hold time after (Repeated) Start Condition
TSU:STA – Repeated Start Condition setup time
TSU:STO – Stop Condition setup time
TTIMEOUT – Detect clock low timeout
– Send Byte
– Receive byte
– Write Byte
– Read Byte
– Write Word
– Read Word
– Block Write
– Block Read
– Process Call
– Block Write Block Read Process Call
VIH – HIGH-level input voltage
TF – Clock/Data Fall Time
TR – Clock/Data Rise Time
– Skip a clock bit
– Send additional clock bit
– Skip START/STOP/RP-START/BYTE/ACK
– Send NACK instead of ACK for a Read Byte
– Send ACK instead of NACK for last Read Byte
– Send incorrect PEC byte
– Send invalid Data byte
TLOW:SEXT – Cumulative clock low extend time (slave device)
TLOW:MEXT – Cumulative clock low extend time (master device)
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