PMBus (Power Management Bus) Protocol Validation

Soliton’s PMBus Protocol Validation Suite can generate a full-fledged timing, voltage, clock stretch behavior, and fault tolerance report for the PMBus interface on a chip. The solution can skew bus timing parameters, sweep bus voltage levels, verify and measure clock stretching, induce bus timeout, induce spikes/glitches, induce packet formation faults and measure bus timing parameters. The solution is compatible with PMBus specification version 1.3.1.

Customers can also ship 3 DUT boards containing their desired slave device to Soliton Technologies and we will characterize the DUT and send the customer a comprehensive PMBus Validation Report within a cycle time of 1 week.

Generating a full fledged timing, voltage, clock stretch behavior and fault tolerance report for the PMBus interface on a chip

PMBus Validation Suite Features:

  1. Supported data transfer formats

    – Send Byte
    – Receive byte
    – Write Byte
    – Read Byte
    – Write Word
    – Read Word
    – Block Write
    – Block Read
    – Process Call
    – Block Write Block Read Process Call
    – Group Command Protocol
    – Extended Command Read Byte
    – Extended Command Write Byte Protocol
    – Extended Command Read Word Protocol
    – Extended Command Write Word Protocol

  2. Option to send commands with or without PEC (Packet Error Check)
  3. Supports different bus speed

    – 100kHz
    – 400kHz
    – 1MHz

  4. Configure and sweep each bus timing parameter from the Min to the Max range

    FSMB – Operating Frequency
    TLOW – Clock low period
    THIGH – Clock high period
    THD:DAT – Data hold time
    TSU:DAT – Data setup time
    TBUF – Bus free time between Stop and Start Condition
    THD:STA – Hold time after (Repeated) Start Condition
    TSU:STA – Repeated Start Condition setup time
    TSU:STO – Stop Condition setup time
    TTIMEOUT – Detect clock low timeout

  5. Ability to detect and allow clock stretching by the device

    Soliton's PMBus Validation service has ability to stretch the Clock low to induce clock stretching and bus timeout in PMBus I2C Protocol

  6. Ability to stretch the Clock low to induce clock stretching
  7. Measures cumulative clock stretching time

    TLOW:SEXT – Cumulative clock low extend time (slave device)
    TLOW:MEXT – Cumulative clock low extend time (master device)

  8. Sweeps and measures Rise time and Fall time

    TF – Clock/Data Fall Time
    TR – Clock/Data Rise Time

  9. Supports voltage sweep

    VIH – HIGH-level input voltage

  10. Support for 7-bit and 10-bit slave addressing
  11. Ability to induce faults in the communication

    – Skip a clock bit
    – Send additional clock bit
    – Send NACK instead of ACK for a Read Byte
    – Send ACK instead of NACK for last Read Byte
    – Send incorrect PEC byte
    – Send invalid Data byte

  12. Ability to detect faults by sensing SMBALERT# signal after each transaction


    • Semiconductor Chip Manufacturers making PMBus Slave Devices
    • SMPS Manufacturers looking for a tool for PMBus Compliance, PMBus Validation, IPMI Validation, IPMB Validation, SMPS Interface Validation, SMPS Protocol Validation or SMPS Digital validation, ATCA Validation, SMPS testing
Please contact [email protected] for more details.